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# NTU Computer Engineering Review: CZ1005 Digital Logic

Both lecturers are really good, very clear. I didn’t attend or watch any of the lectures. But I watched all the pre-recorded lectures. For this module, I quite like the system where all the pre-recorded lectures (all contents for this module) are uploaded at the beginning. You can take your time to watch them at your own pace, but there is a recommended time to watch them (e.g. which week to watch which video). The real life lectures (there are uploaded recordings of these too) are mostly for recaps only, and maybe some lab info.

The only thing I don’t like about the pre-recorded lectures is that it is so slowwwwwwww (the spoken) and there is no x1.5 or x2 speed button!! (And I can’t download it too!!!) I kept falling asleep while watching it :(:(:(.

I think the tutorials are really useful to attend. (I think I skipped 3 of them though, due to various reasons, such as, it is a Friday class, or I had Laos Project fundraising, or sometimes Cryptography module got cancelled and I went home on Thursday instead etc). For this mod, the uploaded answers are not as pretty. It is like tutorial scribbles which you can probably understand better if you attend the tutorials. So the answers are not really printable.

All labs are compulsory, with a 8-mark graded quiz at the end. I can’t believe I lost so many marks for the quizzes. For example, it asked for the 2’s complement representation of +40, I was probably too noob, but I thought they wanted 2’s complement of +40 which is the -40 one. So I typed the 2’s complement representation of -40 instead, which costs me 2 marks. The other 3 marks I guess I “legitly” lost them hahaha.

Final paper was finished in 1hr 50mins. It was okay… but for one of the questions, I was not sure about the order of things in “synchronous always block”. It was said that order matters. But then I’m not sure what happens when i do a<=b then b<=a (does this b get the old a or the new a (which is b now). I was tempted to create another register… but then the qn says according to the circuit as shown in the figure which has only 2 registers… so… I decided to wire it outside then. I assumed the synchronous always block will “finish running” before the assign statements get “done” outside, since it is supposed to act like solid wire.